In a memory, memory cells are located at intersections of word lines and bit line pairs. A row decoder activates one word line, and memory cells located on the activated word line provide their contents to corresponding bit line pairs. Then column decoding selects at least one bit line pair, and the number of bit line pairs selected depends on the organization of the memory. A selected memory cell is located at an intersection of an activated word line and a selected bit line pair. During a read cycle, a selected bit line pair is coupled to a data line pair. A sense amplifier detects the contents of the selected memory cell on the data line pair and provides it to additional circuitry for output. The speed of the sensing operation determines the access time of the memory.
Memories continually require faster access times to be commercially competitive. At the same time, other constraints like power consumption exist. Integrated circuit fabrication techniques have made both bipolar transistors and CMOS transistors (BICMOS) manufacturable on a single integrated circuit. BICMOS circuits are generally faster than CMOS circuits, but consume more power. Thus, a memory sensing scheme using CMOS transistors only may no longer be desirable when BICMOS technology exists.